The present invention relates generally to digital filters. More specifically, the present invention relates to digital decimation filters.
Delta-sigma analog to digital (A/D) converters are popular in a variety of applications including telecommunications, test equipment, and sound reproduction. In general, delta-sigma A/D converters have a delta modulator and a summation unit. The delta modulator of a delta-sigma A/D converter generates a digital signal based on the difference between an input voltage and a reference voltage.
The summation unit of a delta-sigma A/D converter consists of a counter to summate the pulses generated by the delta modulator. The summation unit is reset every A/D cycle. The output of the counter is latched at the end of every A/D cycle.
The summation unit may also be implemented using a digital low-pass filter followed by a decimator to lower the sampling rate. See J. C. Candy, Decimation for Sigma-Delta Modulation, IEEE Transactions on Communications, vol. 34, pp. 72-76 (January 1986). A sinc (or comb) filter may be used to perform this filtration and decimation. The sinc filter is a low-pass, finite impulse response (FIR) decimation filter. The sinc filter has the transfer function:             H      ⁡              (        z        )              =                            (                                    1              M                        ⁢                          (                              1                +                                  z                                      -                    1                                                  +                …                +                                  z                                      -                                          (                                              M                        -                        1                                            )                                                                                  )                                )                L            =                        (                                    1              -                              z                                  -                  M                                                                    M              ⁡                              (                                  1                  -                                      z                                          -                      1                                                                      )                                              )                L              ,
where L is the order of the sinc filter and M is the oversampling ratio of the sinc filter. Functionally, the sinc filter takes a moving average of the input over time.
One implementation of the sinc filter known as the Hogenaur structure is illustrated in FIG. 1. A Hogenaur structure sinc filter consists of a series of cascaded accumulators followed by a series of cascaded differentiators and a scaling factor which is just a shift. See E. B. Hogenauer, An Economical Class of Digital Filters for Decimation and Interpolation, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-29(2), pp. 155-162 (April 1981). Resampling at the lower (Nyquist) frequency is performed between the differentiators and the integrators. See id. This resampling allows the integrators to operate at a higher frequency, providing the M (oversampling) factor in the numerator of the transfer function, while the differentiators operate at a lower frequency. See id.
A Lth order sinc filter has M packets of L zeros located at the same position in the frequency domain, and each packet is separated by the Nyquist frequency. See id. For example, FIG. 1A shows the frequency response of a sinc filter where M=32, L=4, and the Nyquist frequency fs=60 Hz. The illustrated sinc filter has 32 packets of 4 zeros at multiples of 60 Hz.
In a sinc filter, the position of the frequency notches is dependant on the frequency of the oscillator. However, the frequency of oscillators may vary with temperature and supply voltage. There are a number of methods to deal with or compensate for this dependence on the frequency of the oscillator.
One technique to create a stable sinc filter over a wide range of temperatures and supply voltages is to build an oscillator with the desired precision over the fill range of temperatures and supply voltages. See LinearTech, LTC 2400 Datasheet (2001).
A second technique is to use a combination of different types of filters (i.e. multi-stage filters) for greater efficiency. In one example of this technique, a simple comb filter is used in the front-end at the higher rate. The comb filter is followed by half-band FIR or infinite impulse response (IIR) filters that are more complex than the comb filter, but where the sampling rate is lower. A digital signal processor (DSP) is commonly used to implement the more complex FIR filters, giving them very sharp frequency notches. See Steven R. Norsworthy, Richard Schreir, and Gabor C. Temes, Delta-Sigma Data Converters Theory, Design and Simulation (IEEE Press 1997).
A third technique is to modify the transfer function of the sinc filter by adding a little perturbation so that the filter creates frequency notches wider than the simple sinc filter. In one example of this technique, a perturbation is added in the accumulations preformed by the filter so that its coefficients are slightly different than the original ones. Therefore, the zeros are slightly moved and staggered. See Letzia Lo Presti, Efficient Modified-Sinc Filters for Sigma-Delta A/D Converters, Analog and Digital Processing, vol. 47, no. 11 (November 2000).
In accordance with the teachings of the present invention, a digital decimation filter including an integrator, a differentiator, a scaling unit, and a control unit is provided. In an exemplary embodiment of the invention, the integrator is adapted to receive an input signal where the input signal includes one or more frequency components. The differentiator is coupled to the integrator and includes a programmable counter. The scaling unit is coupled to the differentiator and is adapted to produce an output signal. The control unit is preferably coupled to the integrator, the differentiator, and the scaling unit. The control unit is preferably adapted to store one or more programmable frequency notches, wherein the control unit activates the programmable counter such that the output signal is a filtered version of the input signal where the frequency components corresponding to the programmable frequency notches are attenuated.
In another exemplary embodiment of the present invention, the programmable counter is adapted to perform a function based on the input and a value stored in the differentiator, in response to a signal from the control unit. Preferably, the programmable counter performs a differentiation.
In another exemplary embodiment of the present invention, the control unit includes one or more registers and each register is adapted to store a value representing a frequency notch of the digital decimation filter. Preferably, the control unit includes a data bus coupled to the registers which is operable to load values from or store values to the registers. Preferably, the control unit includes a counter having a current value and one or more comparators, where each comparator is adapted to compare the value stored in one of the registers with the current value of the counter.
In another exemplary embodiment of the present invention, the scaling unit includes a register, a shifter, and an adder. The register has an input adapted to receive data from the differentiator and an output. The shifter has an input adapted to receive data from the register, an output, and a binary value. The shifter is operable to shift the binary value. The adder has a first input adapted to receive data from the shifter and an output.
In another aspect, the present invention provides a method of filtering a signal. An example of the method includes integrating the signal to produce an integrated signal and selectively differentiating the integrated signal using a programmable counter to produce a differentiated signal, and resampling the integrated signal at a frequency lower than a clock frequency. The integrated signal is differentiated according to one or more programmable frequency notches. This exemplary method preferably includes comparing a current value with one or more stored frequency notch values and performing the differentiation if the current value is equal to a stored frequency notch value. This exemplary method preferably includes scaling the differentiated signal so that the filter achieves a desired gain for a DC signal. The exemplary method preferably accomplishes the scaling using a register, a shifter, and an adder. The exemplary method preferably substantially achieves a gain of 0 dB for DC signals.
In another aspect, the present invention provides a delta-sigma analog-to-digital (A/D) converter. An exemplary embodiment of the converter includes a digital decimation filter. The digital decimation filter is adapted to receive an input and produce an output The digital decimation filter includes an integrator and a differentiator coupled together. The differentiator includes a programmable counter that is adapted to selectively differentiate an input signal according to one or more programmable frequency notches. The exemplary converter preferably includes a plurality of registers. Each register is adapted to store a value of a frequency notch of the digital decimation filter. The exemplary converter preferably includes a counter and a plurality of comparators. The counter has a current value. Each of the plurality of comparators is operable to compare the value of respective ones of the registers with the current value of the counter and produce an output based on the comparison. The exemplary comparator preferably includes a scaling unit. The scaling unit is operable to receive a signal from the differentiator as an input and produce an output, where the output is a scaled version of the input. Preferably, the scaling unit has a 0 dB gain when a DC signal is input to the converter. The scaling unit preferably includes a programmable shifter operable to shift data bitwise left or right.
In another aspect, the present invention provides a signal processing apparatus including a digital decimation filter. In one exemplary embodiment of the invention, the digital decimation filter includes an integrator, a differentiator, a control unit, and a scaling unit. The integrator is coupled to the differentiator. The differentiator is coupled to the scaling unit. The control unit is coupled to the integrator, the differentiator, and the scaling unit. The differentiator includes a programmable counter. Preferably, the signal processing apparatus includes an input signal that has one or more frequency components and the control unit has one or more frequency notches. In an exemplary embodiment of the signal processing apparatus, the control unit activates the differentiator such that the digital decimation filter attenuates the frequency component corresponding to one of the frequency notches.
Features and advantages of the invention will be apparent from the following description of the embodiments, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.